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Location: Lahore/Islamabad/Karachi
Experience: 1-3 Years of Experience
Qualification: Bachelors/Masters in Computer/Electrical/Electronic Engineering
Responsibilities/Requirements:
- Turning design documentation into a verification plan & executing the plan
- Defining & developing verification environment and test cases
- Writing test cases, simulating them and debugging simulation failures
- Defining & running regressions and triaging regression failures
- Document failures & driving them to closure
- Interacting with architects and design engineers
- Experience in UVM and Verilog is required
- Knowledge of TCL/Perl in a unix environment is must
- Theoretical knowledge of object oriented language (C++ or Java or Python)
- Knowledge of Digital Logic, Computer Architecture, Microprocessor Design, Verilog, and Digital VLSI Design
Perks:
- International Training
- Long-term career pathway
- Market competitive salary
- Health Life & Group Life Insurance
- Friendly and a great learning work environment
- Mentored & trained by highly skilled people
Job Type: Contract
Contract length: 6 months
Pay: Rs65,000.00 - Rs75,000.00 per month
Application Question(s):
- Do you have knowledge/experience in UVM and Verilog?
- Do you have knowledge/experience in C++ or Java or Python?
- Do you have knowledge/experience in Digital Logic, Computer Architecture, Microprocessor Design, Verilog, and Digital VLSI Design?
- Important Question to proceed with your profile: Where do you live?
- Important Question to proceed with your profile: Can you work in Islamabad/Lahore/karachi?
- Important Question to proceed with your profile: Kindly provide me with your correct email address:
- Important Question to proceed with your profile: Kindly provide me with your correct contact number:
- What is your expected salary?
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